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Lattice Semiconductor
Functional Description
Management Interface Read/Write Operation
During a write operation, mdio_en is asserted and the data is transmitted on mdo. During a read operation,
mdio_en is asserted while the address is being transferred. Once this is done, it is de-asserted for rest of the trans-
fer enabling the PHY to deliver data on mdi.
Figure 2-18. Management Interface Read and Write Operations
mdc
mdio_en
mdo
address and write data
address of register being read
mdi
WRITE
OPERATION
READ
OPERATION
read data
GMII Transmit and Receive Operations (1G mode and Gigabit MAC Option)
txd and tx_en are driven synchronous to the gtx_clk during transmit operations. When the frame being transmitted
has an error, tx_er is asserted.
When receiving data, rxd and rx_en are sampled on the rising edge of rx_clk. An error in the frame is indicated
when rx_er is asserted.
Figure 2-19. GMII Transmit and Receive Operations
gtx_clk
tx_en
txd[0:7]
tx_er
rx_clk
rx_en
rxd[0:7]
rx_er
IPUG51_03.0, December 2010
VALID FRAME DATA
FRAME WITHOUT
ERROR
VALID FRAME DATA
FRAME WITHOUT
ERROR
36
VALID FRAME DATA
FRAME WITH
ERROR
VALID FRAME DATA
FRAME WITH
ERROR
Tri-Speed Ethernet MAC User’s Guide
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相关PDF资料
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相关代理商/技术参数
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